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MC13017
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NTSC/PAL Chroma 10 Color TV and Timebase Processor
The MC13017 consists of all the necessary circuits for TV NTSC/PAL decoding and timebase processing. It forms a kit set with the MC44301 VIF and the TDA3190 Sound IF and Power for a low cost, high performance CTV system. * On-Chip Sync Separator
NTSC/PAL CHROMA 10 COLOR TV and TIMEBASE PROCESSOR
SEMICONDUCTOR TECHNICAL DATA
* * * * * * * * * * * *
Dual Loop Horizontal Timebase Direct Locked Vertical Counter X-Ray Protection Noise Blanking on Sync Separator NTSC/PAL Color Decoding Direct Interface with SECAM TDA3030B 4.43/3.579 MHz Crystal Reference Three DC High Impedance Control Outputs for Contrast, Brightness, and Saturation 12 V Supply Vertical Ramp Buffer Output Sandcastle Output Hue Control PIN CONNECTIONS
VCC3 1 V. Gnd 2 V. Feedback 3 V. Out 4 Buffer Ramp 5 Ramp Cap 6 V. Height 7 Sync Sep Cap 8 Unit V 5C C V Sync I/P 9 Luma I/P 10 VCC1 + 12 V 11 Hue 12 Chroma I/P 13 ACC 14 DL E 15 DL C 16 Sat 17 ID 18 V I/P 19 U I/P 20 (Top View) 15 10 0 to +70 - 55 to +125 8.0 4.0 40 VCC2 39 H. Gnd 38 H. O/P 37 PD2 36 H. Flyback 35 PD1 34 H. Freq 33 X-Ray 32 Contrast 31 Brightness 30 Sandcastle Pulse 29 R O/P 28 G O/P 27 B O/P 26 DC Ref & BL 25 Gnd 24 Xtal FB 23 Xtal Drive 22 VCO FLT 21 90 FLT
40 1
P SUFFIX PLASTIC PACKAGE CASE 711
MAXIMUM RATINGS (TA = 25C, unless otherwise noted.)
Rating Power Supply Voltages Operating Temperature Range Storage Temperature Range Horizontal Output Voltage Vertical Output Voltage Symbol VCC1, VCC3 VCC2 TA Tstg VOH VOV Value
ORDERING INFORMATION
Device MC13017P Operating Temperature Range TA = 0 to +70C Package Plastic DIP
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
(c) Motorola, Inc. 1995
MOTOROLA ANALOG IC DEVICE DATA
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MC13017
PIN FUNCTION DESCRIPTION
Pin 1 2 3 4 5 6 7 8, 9 Function VCC3 Vert Gnd Vert Feedback Vert Out Buffer Ramp Ramp Cap Vert Height Sync Sep Cap, Sync I/P +12 V supply for VCC2 power regulator. Vertical output analog ground. The Ramp on Pin 6 is internally inverted, level shifted and subtracted from the input to Pin 3. The result appears as an output on an open collector at Pin 4. Vertical ramp output to external vertical power drive. The vertical buffer ramp output of Pin 6. The external cap is charged by a current controlled through vertical height control Pin 7 to produce a vertical ramp. The discharge of the cap is controlled internally by the vertical counter. Current input for vertical height control. Sync separator input is a NPN transistor stage with the signal presented at its base with a peak level of about 4.0 V. The emitter is brought out to Pin 8 through a 200 resistor so that a capacitor with a series resistor may be connected. The circuit behaves as a peak detector with a slicing level controlled by the choice of charge and discharge resistors. An additional time constant is connected through a diode to prevent the slice level from riding up on the field sync. +12 V supply for chroma. This is Hue control for NTSC system. It should be connected to VCC1 at PAL system. When voltage at Pin 12 is smaller than 8.0 V, NTSC mode is selected. Delay line drive open emitter terminal. Delay line drive open collector terminal. An external filter cap is connected at this pin for ID circuit. V, U inputs after delay line to detectors. 90 phase shifter filter. Color reference VCO filter. A 4.43 MHz (PAL), or 3.579 MHz (NTSC) crystal is connected to the internal VCO for color subcarrier reference frequency. The Sandcastle Pulse Output is delivered through 200 from an emitter-follower with 10 k pull-down. The blanking duration is determined by the applied flyback pulse. The burst gate determined by the second half of the flyback levels are: Blanking (4.0 V), Burst Gate (11 V). Horizontal phase detector current output. The PLL 1 is locked to the sync input with 2H oscillator. Horizontal flyback, a positive input pulse exceeded threshold of 1.0 V is required, input impedance is between 600 and 2.0 k so that a minimum of 0.5 mA current is needed to exceed the threshold voltage. The recommended peak current is 2.0 mA. Second horizontal phase detector current output. The function of PLL 2 is to adjust the horizontal drive in order to maintain the flyback in phase with the oscillator. This is a saturated NPN transistor with a 2.0 k internal load to regulate supply VCC2. Horizontal analog output grounding should be connected nearby the external horizontal output stage. Regulated supply to horizontal timebase section. A diode is in series with 270 from VCC3 + 12 V to block the high voltage startup supply of 10 mA for horizontal oscillator. Description
11 12 15 16 18 19, 20 21 22 23 24 30
VCC1 Hue DL E DL C ID Filter V, U 90 Filter VCO Filter Xtal 2 Xtal 1 Sandcastle Pulse Output PD1 Horiz Flyback
35 36
37 38 39 40
PD2 Horiz Out Horiz Gnd VCC2
2
MOTOROLA ANALOG IC DEVICE DATA
MC13017
OUTLINE DIMENSIONS
P SUFFIX PLASTIC PACKAGE CASE 711-03 ISSUE C
40 21
B
1 20
NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 51.69 52.45 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0_ 15_ 0.51 1.02 INCHES MIN MAX 2.035 2.065 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0_ 15_ 0.020 0.040
A N
L C
J H G F D K
SEATING PLANE
M
MOTOROLA ANALOG IC DEVICE DATA
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MC13017
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MC13017/D MOTOROLA ANALOG IC DEVICE DATA
*MC13017/D*

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